1. Field of the Invention
The present invention relates to organic electroluminescent display devices, and more particularly, to an active matrix electroluminescent display devices having thin film transistors.
2. Discussion of the Related Art
As an information age has been evolved rapidly, a necessity for flat panel displays, which have advantages such as thinness, lightweight and lower power consumption, has been increased. Accordingly, various flat panel display (FPD) devices such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission display devices and electro luminescence display (ELD) devices have been researched and have been developed.
Among many kinds of FPD devices, the electroluminescence display (ELD) device makes use of electro luminescence phenomenon in which light is generated when an electric field of certain intensity is applied to a fluorescent substance. The electroluminescence display (ELD) devices can be classified into inorganic electroluminescence display (ELD) device and organic electroluminescent display (ELD) device depending on a source that excites careers. The organic electroluminescent display (ELD) device has drawn attention as a displaying device for natural colors because it can display every color in a range of a visible light and has a high brightness and a low voltage.
In addition, because the organic electroluminescence display (ELD) device is a self-luminescent, it has a high contrast ratio and is suitable for an ultra-thin type display device. Moreover, because it has a simple manufacturing process, the degree of environmental contamination is relatively low. Besides, the organic electroluminescence display (ELD) device has a few microseconds (μs) response time, so that it is suitable for displaying moving images. The organic electroluminescence display (ELD) device has no limit in a viewing angle and is stable in low temperature condition. Because it is driven with a relatively low voltage between 5V and 15V, a manufacturing and design of a driving circuit is easy.
A structure of the organic electroluminescent display (ELD) device is similar to that of the inorganic electroluminescence display (ELD) device, but the light-emitting theory of the organic ELD device is different from that of the inorganic ELD device. That is, the organic electroluminescent display (ELD) device emits light by a recombination of an electron and a hole, and thus it is often referred to as an organic light emitting diode (OLED).
Recently, active matrix type of ELD, in which a plurality of pixels is arranged in a matrix form and a thin film transistor is connected thereto, has been widely applied to the flat panel display devices. The active matrix type is also applied to the organic electroluminescent display (ELD) device and this is referred to as an active matrix organic electroluminescent display (ELD) device.
FIG. 1 is an equivalent circuit diagram showing a basic pixel structure of a conventional active matrix organic electro luminescent display (ELD) device.
In FIG. 1, a pixel of the active matrix organic electroluminescent display device has a switching thin film transistor 4, a driving thin film transistor 5, a storage capacitor 6 and a light emitting diode (LED) 7. The switching thin film transistor 4 and the driving thin film transistor 5 are comprised of p-type polycrystalline silicon thin film transistor. A gate electrode of the switching thin film transistor 4 is connected to the gate line 1 and a source electrode of the switching thin film transistor 4 is connected to the data line 2. A drain electrode of the switching thin film transistor 4 is connected to a gate electrode of the driving thin film transistor 5, and a drain electrode of the driving thin film transistor 5 is connected to an anode electrode of the light emitting diode (LED) 7. A cathode electrode of the light emitting diode (LED) 7 is grounded. A source electrode of the driving thin film transistor 5 is connected to a power line 3, and a storage capacitor 6 is connected to the gate electrode and the source electrode of the driving thin film transistor 5.
In the pixel structure shown in FIG. 1, if a scanning signal is applied to the gate line 1, the switching thin film transistor 4 is turned on and an image signal from the data line 2 is stored into the storage capacitor 6 through the switching thin film transistor 4. If the image signal is applied to the gate electrode of the driving thin film transistor 5, the driving thin film transistor 5 is turned on and thus the light emitting diode (LED) 7 emits light. Luminance of the light emitting diode (LED) 7 is controlled by varying an electric current of the light emitting diode (LED) 7. The storage capacitor 6 serves to keep a gate voltage of the driving thin film transistor 5 constant while the switching thin film transistor 4 is turned off. That is, because the driving thin film transistor 5 can be driven by a stored voltage in the storage capacitor 6 even when the switch thin film transistor 4 is turned off, the electric current can keep flowing into the light emitting diode (LED) 7, and thus the light emitting diode (LED) emits light until a next image signal comes in.
FIG. 2 is a schematic cross-sectional view of a related art active matrix organic electroluminescent display device. FIG. 2 shows an organic light emitting diode, a storage capacitor and a driving thin film transistor. Moreover, a bottom emission type, in which light is emitted through an anode of a lower electrode, is adopted.
In FIG. 2, a buffer layer 11 is formed on a substrate, and then a first polycrystalline silicon layer having first to third portions 12a, 12b and 12c and a second polycrystalline silicon layer 13a are formed on the buffer layer 11. The first polycrystalline silicon layer is divided into the first portion 12a (i.e., an active region) where impurities are not doped and the second and third portions 12b and 12c (i.e., respectively, a drain region and a source region) where the impurities are doped. The second polycrystalline silicon layer 13a becomes one of the capacitor electrodes. A gate insulation layer 14 is disposed on the active region 12a, and a gate electrode 15 is disposed on the gate insulation layer 14. A first interlayer insulator 16 is formed on the gate electrode 15 and on the gate insulation layer 14 while covering the drain and source regions 12b and 12c and the second polycrystalline silicon layer 13a. A power line 17 is disposed on the first interlayer insulator 16 particularly above the second polycrystalline silicon layer 13a (i.e., the capacitor electrode). Although not shown in FIG. 2, the power line 17 extends as a line in one direction. The power line 17 and the second polycrystalline silicon layer 13a with the first interlayer insulator 16. therebetween form a storage capacitor. A second interlayer insulator 18 is formed on the first interlayer insulator 16, covering the power line 17.
Meanwhile, first and second contact holes 18a and 18b, which penetrate both the first and second interlayer insulators 16 and 18, expose the drain region 12b and source region 12c, respectively. Additionally, a third contact hole 18c, which penetrates the second interlayer insulator 18, is formed and exposes a portion of the power line 17. A drain electrode 19a and a source electrode 19b are formed on the second interlayer insulator 18. The drain electrode 19a contacts the drain region 12b through the first contact hole 18a. The source electrode 19b contacts both the source region 12c and the power line 17, respectively, through the second contact hole 18b and through the third contact hole 18c, respectively. A first passivation layer 20 is formed on the drain and source electrodes 19a and 19b and on the exposed portions of the second interlayer insulator 18. The first passivation layer 20 has a fourth contact hole 20a that exposes a portion of the drain electrode 19a. An anode electrode 21 that is made of a transparent conductive material is disposed on the first passivation layer 20 and contacts the drain electrode 19a through the fourth contact hole 20a. A second passivation layer 22 is formed on the anode electrode 21 and on the exposed portions of the first passivation layer 20. The second passivation layer 22 has a well 22a that exposes a portion of the anode electrode 21. An electroluminescent layer 23 is formed on the second passivation layer 22 and into the well 22a. A cathode electrode 24 is formed entirely over the surface including on the exposed portions of the second passivation layer 22 and on the electroluminescent layer 23. The cathode electrode 24 is formed of an opaque metallic conductive material.
In the active matrix organic electroluminescent display device illustrated in FIG. 2, the anode electrode 21 is formed of the transparent conductive material, while the cathode electrode 24 is formed of the opaque conductive material. Thus, the light emitted from the organic electroluminescent layer 23 is released in a bottom direction. Such device is called the bottom emission type.
FIGS. 3A to 3I are cross-sectional views illustrating a fabricating process of the active matrix organic electroluminescent display device of FIG. 2. Many of the patterns shown in FIGS. 3A to 3G are formed through a photolithography process of photoresist (PR) coating, aligning, exposing and developing steps using a mask.
In FIG. 3A, after a buffer layer 11 is formed on an entire surface of a substrate 10, first and second semiconductor layers 12 and 13 of polycrystalline silicon are formed on the buffer layer 11 through a first mask process. The first and second polycrystalline semiconductor layers 12 and 13 have island shapes.
In FIG. 3B, an insulator of silicon nitride or silicon oxide and a conductive material of metal are sequentially deposited on the first polycrystalline silicon layer 12 and then patterned using a second mask, thereby sequentially forming a gate insulation layer 12 and a gate electrode 15 on the first polycrystalline semiconductor layer 12. Thereafter, impurities such as p-type ions are doped on the exposed portions of the first and second polycrystalline semiconductor layers 12 and 13. During doping, the gate electrode 15 acts as a mask so that the first polycrystalline semiconductor layer 12 is divided into an active region 12a where the impurities are not doped and drain and source regions 12b and 12c where the impurities are doped. Further, the second polycrystalline semiconductor layer 13 on which the impurities are fully doped becomes a capacitor electrode 13a. The drain and source regions 12b and 12c are located on both sides of the active region 12a. 
Referring to FIG. 3C, a first interlayer insulator 16 is formed on the entire surface of the buffer layer 11 so as to cover the gate electrode 15, the drain and source regions 12b and 12c, and the capacitor electrode 13a. After forming the first interlayer insulator 16 over the entire surface of the substrate 10, a power line 17 of metal is formed through a third mask process on the first interlayer insulator 16 particularly to overlap the capacitor electrode 13a. Since the power line 17 is formed right above the capacitor electrode 13a, it forms a storage capacitor with the capacitor electrode 13a and the interposed first interlayer insulator 16.
In FIG. 3D, a second interlayer insulator 18 is formed on the first interlayer insulator 16 and on the power line 17. Thereafter, first to third contact holes 18a, 18b and 18c are formed using a fourth mask process. The first contact hole 18a exposes the drain region 12b, the second contact hole 18b exposes the source region 12c, and the third contact hole 18c exposes the power line 17.
In FIG. 3E, a metal layer is formed on the second passivation layer 18 and then patterned through a fifth mask process, thereby forming a drain electrode 19a and a source electrode 19b. The drain electrode 19a contacts the drain region 12b through the first contact hole 18a, while the source electrode 19b contacts the source region 12c through the second contact hole 18b. Furthermore, the source electrode 19b contacts the power line 17 through the third contact hole 18c. 
Through the previously described process, a driving thin film transistor having the semiconductor layer 12, the gate electrode 15, the drain and source electrodes 19a and 19b is completed. Moreover, a region corresponding to the power line 17 and the capacitor electrode 13a forms the storage capacitor. Although not shown in FIG. 3E, but shown in FIG. 1, the storage electrode 13 is connected to the gate electrode 15 of the driving thin film transistor, and the power line 17 is parallel to the signal line.
In FIG. 3F, a first passivation layer 20 having a fourth contact hole 20a resulting from a sixth mask process is formed on the second interlayer insulator while covering the drain and source electrodes 19a and 19b. The fourth contact hole 20a exposes a portion of the drain electrode 19a. 
In FIG. 3G, a transparent conductive material is deposited on the first passivation layer 20 and then patterned using a seventh mask process, thereby forming an anode electrode 21 that contacts the drain electrode 19a through the fourth contact hole 20a. 
In FIG. 3H, a second passivation layer 22 is formed on the anode electrode 21 and on the exposed portion of the first passivation layer 20. Thereafter, the second passivation layer 22 is patterned using an eighth mask process, thereby forming a well 22a that exposes a portion of the anode electrode 21.
Now in FIG. 3I, an organic electroluminescent layer 23 is formed on the second passivation layer to contact the anode electrode 21 through the well 22a. Thereafter, a cathode electrode 24 is formed on the organic electroluminescent layer 23 and on the exposed portion of the second passivation layer 22. The cathode electrode 24 entirely covers the substrate 10.
In the above-mentioned processes forming the organic electroluminescent display device, a plurality of thin film depositions are repeated, and moreover a plurality of photolithography processes that use masks are also repeated many times. Therefore, these repetitions increase the mask process. Since the photolithography process includes a rinsing process, a photoresist deposition process, an exposure process, a developing process, an etching process, etc., the manufacturing time and the cost of production can be reduced if only one mask process is omitted. The organic electroluminescent display device described with reference to FIGS. 3A to 3I, however, requires eight masks, resulting in a decreased production yield and increased cost of production. Moreover, the more masks the organic electroluminescent display device requires, the more defects the fabrication process creates.
Additionally, since the active matrix organic electroluminescent display device of the related art has a capacitor electrode that is an opaque material, it has a decreased luminant area and a reduced aperture ratio. In order to overcome these problems, the current density should be raised to increase the luminance of the device, thereby causing a decreased life span of the organic electroluminescent display device.
Furthermore, since the organic electro luminescent display device of the related art has the power line in a shape of line, the power line is easily deteriorated and damaged and the active matrix organic electroluminescent display device do not display images uniformly.